`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:33:10 04/05/2011 
// Design Name: 
// Module Name:    MEMtoWB_Buffer 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module MEMtoWB_Buffer(clk, RegWriteIn, MemtoRegIn, readDataIn, ALUresultIn, writeDstIn,
	RegWriteOut, MemtoRegOut, readDataOut, ALUresultOut, writeDstOut);
	
	input clk, RegWriteIn, MemtoRegIn;
	input [15:0] readDataIn, ALUresultIn;
	input [3:0] writeDstIn;
	
	output RegWriteOut, MemtoRegOut;
	output [15:0] readDataOut, ALUresultOut;
	output [3:0] writeDstOut;
	
	reg RegWriteOut, MemtoRegOut;
	reg [15:0] readDataOut, ALUresultOut;
	reg [3:0] writeDstOut;
	
	always @ (posedge clk)
	begin
		RegWriteOut <= RegWriteIn;
		MemtoRegOut <= MemtoRegIn;
		readDataOut <= readDataIn;
		ALUresultOut <= ALUresultIn;
		writeDstOut <= writeDstIn;
	end


endmodule
